The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices with improved planarity, reduced defects and reduced leakage between lines. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures with improved reliability.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance and capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometric shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section. The entire opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition Cu has improved electrical properties, vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), titanium-titanium nitride (Tixe2x80x94TiN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
In conventional CMP techniques, a wafer carrier assembly is rotated in contact with a polishing pad in a CMP apparatus. The polishing pad is mounted on a rotating turntable or platen, or moving above a stationary polishing table, driven by an external driving force. The wafers are typically mounted on a carrier or polishing head which provides a controllable pressure urging the wafers against the polishing pad. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of each thin semiconductor wafer and the polishing pad while dispersing a polishing chemical with or without abrasive particles in a reactive solution to effect both chemical activity and mechanical activity while applying a force between the wafer and a polishing pad.
It is extremely difficult to planarize a Cu surface, as by CMP of a damascene inlay, without generating a high degree of surface defects, such as corrosion, scratches, pitting and embedded abrasive particles. A dense array of Cu features is typically formed in an interlayer dielectric, such as a silicon oxide layer, by a damascene technique wherein trenches are initially formed. A barrier layer, such as a Ta-containing layer, e.g., Ta, TaN, is then deposited lining the trenches and on the upper surface of the silicon oxide interlayer dielectric. Cu or a Cu alloy is then deposited, as by electroplating, electroless plating, physical vapor deposition (PVD) at a temperature of about 50xc2x0 C. to about 150xc2x0 C. or chemical vapor deposition (CVD) at a temperature under about 200xc2x0 C., typically at a thickness of about 8,000 xc3x85 to about 18,000 xc3x85. CMP is then conducted to remove the Cu or Cu alloy overburden stopping on the barrier layer. Polishing is then continued, as by buffing, employing a mixture of a chemical agent and abrasive particles, to remove the barrier layer. Alternatively, CMP can be conducted directly down to the interlayer dielectric. Buffing is optionally conducted on the interlayer dielectric surface, leaving a Cu or the Cu alloy filling the damascene opening with an exposed surface having a high concentration of defects. These defects include corrosion, e.g., corrosion stains, microscratches, micropitting and surface abrasive particles.
Cu and Cu alloy wafers exhibit a much greater tendency to scratch during planarization than dielectric materials, such as oxides or nitrides. Cu or Cu alloy surfaces corrode very easily and are difficult to passivity in high or low pH aqueous environments. Conventional practices for planarizing Cu or Cu alloys disadvantageously result in a high defect count subsequent to planarization. Conventional wafer cleaning alone cannot completely eliminate such defects which adversely impact device performance and reliability, particularly as device geometries shrink into the deep sub-micron range. Moreover, it is difficult to effectively planarize a surface containing a dense array of Cu or Cu alloy lines without encountering leakage between the lines, particularly as the distance between lines is reduced to satisfy the demand for greater miniaturization.
There exists a need for methodology enabling the planarization of Cu and Cu alloys with a significantly reduced surface defect count and reduced leakage between closely spaced lines. There exists a further need for such enabling methodology that is compatible with conventional CMP and buffing techniques and apparatuses.
An aspect of the present invention is an efficient method of planarizing Cu and Cu alloys with significantly reduced surface defects.
Another aspect of the present invention is an efficient method of treating a planarized surface containing Cu metallization to significantly reduce surface defects and leakage between lines.
Additional aspects and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The aspects of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other aspects are implemented in part by a method of planarizing a surface containing copper (Cu) or a Cu alloy and reducing surface defects; the method comprising: conducting chemical-mechanical polishing (CMP) to planarize the surface; buffing with an abrasive slurry; rinsing with an inhibitor solutions; buffing with a solution to remove copper oxide; and rinsing with an inhibitor.
Another aspect of the present invention is a method of planarizing a wafer surface comprising Cu or a Cu alloy and reducing surface defects, the method comprising the sequential steps: (a) conducting chemical-mechanical polishing (CMP) to planarize the surface; (b) buffing with a solution to remove copper oxides; (c) rinsing with deionized water or an inhibitor solution; (d) buffing with an abrasive slurry; and (e) rinsing with deionized water or an inhibitor solution.
Embodiments of the present invention include employing a solution containing citric acid, ammonium hydroxide and deionized water in step (b) to remove copper oxide, e.g., a solution having a pH of about 3.9 to about 4.1 comprising up to about 26 wt. % citric acid, up to about 5 wt. % of ammonium hydroxide, and deionized water. Embodiments of the present invention also include forming an interconnection structure comprising openings in a silicon oxide interlayer dielectric lined with a barrier layer, such as a Ta-containing barrier layer, e.g., Ta or TaN, and filled with Cu or a Cu alloy, and treating the exposed planarized and buffered upper surface of the Cu or Cu alloy to remove surface defects and effect passivation by sequentially buffing with a solution containing citric acid, ammonium hydroxide and deionized water, rinsing with deionized water or an inhibitor solution, buffing with an abrasive slurry, followed by rinsing with deionized water or an inhibitor solution.
Additional aspects of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.